//----------------------- Output Registers, physical pins
#define PORT_BBA15	PORTL, PL4
#define PORT_BBA16	PORTL, PL5
#define PORT_BBA17	PORTL, PL6
#define PORT_BBA18	PORTL, PL7
#define PORT_BBA	PORTL
#define PORT_BBA_SET(ee)	outb( PORT_BBA, (PORT_BBA & ~0xF0) | (ee << 4))

#define PORT_ARP	PORTL, PL0
#define PORT_ARB	PORTL, PL1
#define PORT_ACE	PORTL, PL2

#define PORT_AWE	PORTG, PG0
#define PORT_AOE	PORTG, PG1
#define PORT_BNKSEL PORTG, PG2

#define PORT_AUX1	PORTE, PE3
#define PORT_AUX2	PORTE, PE4

#define PORT_AUX3	PORTH, PH3
#define PORT_AUX4	PORTH, PH4

#define PORT_BU1	PORTK
#define PORT_BU2	PORTA

#define PORT_LADR	PORTJ
#define PIN_LADR	PINJ
#define DDR_LADR	DDRJ
#define PORT_MADR	PORTC
#define PIN_MADR	PINC
#define DDR_MADR	DDRC
#define PORT_HADR	PORTD
#define PIN_HADR	PIND
#define DDR_HADR	DDRD

#define MMC_CS_DDR	DDRG
#define MMC_CS_PORT	PORTG
#define MMC_CS_PIN	PG5
#define MMC_DDR		DDRE, PE5
#define MMC_CD		PINE, PE5

#define ADDRESS_OE	outb(DDRJ, 0xFF); outb(DDRC, 0xFF); outb(DDRD, inb(DDRD) | 0xE0)
#define ADDRESS_OD	outb(DDRJ, 0x00); outb(DDRC, 0x00); outb(DDRD, inb(DDRD) & 0x1F)

#define ADRMSK_HADR	0xE0

// Sets the Address given x y z byte values
//#define PORT_ADR_SET (z,y,x)	outb(PORT_LADR, x); \ outb(PORT_MADR, y); \ outb(PORT_HADR, inb(PORT_HADR ~ADRMSK_HADR | (z & 0x07)))
#define PORT_ADR_SET_H(x)	outb(PORT_HADR, (inb(PORT_HADR) & ~ADRMSK_HADR) | ((pgm_read_byte(&byteInvert[x]) & ADRMSK_HADR) ))
#define PORT_ADR_SET_M(x)	outb(PORT_MADR, pgm_read_byte(&byteInvert[x]))
#define PORT_ADR_SET_L(x)	outb(PORT_LADR, pgm_read_byte(&byteInvert[x]))
#define PIN_ADR_GET_L		pgm_read_byte(&byteInvert[inb(PIN_LADR)])

#define PORT_ADR_AA			outb(PORT_MADR, 0x40); outb(PORT_LADR, 0x55)
#define PORT_ADR_55			outb(PORT_MADR, 0xA0); outb(PORT_LADR, 0xAA)
//#define PORT_ADR_CMD (y , x)		outb(PORT_LADR, x); \ outb(PORT_MADR, y)

//----------------------- Data Direction Registers
#define DDR_BBA15	DDRL, PL4
#define DDR_BBA16	DDRL, PL5
#define DDR_BBA17	DDRL, PL6
#define DDR_BBA18	DDRL, PL7

#define DDR_ARP		DDRL, PL0
#define DDR_ARB		DDRL, PL1
#define DDR_ACE		DDRL, PL2

#define DDR_AWE		DDRG, PG0
#define DDR_AOE		DDRG, PG1
#define DDR_BNKSEL	DDRG, PG2

#define DDR_AUX1	DDRE, PE3
#define DDR_AUX2	DDRE, PE4

#define DDR_AUX3	DDRH, PH3
#define DDR_AUX4	DDRH, PH4

#define DDR_BU1		DDRK
#define DDR_BU2		DDRA

#define DDR_CCLK	DDRL, PL3

//----------------------- Input Registers
#define PIN_BU1		PINK
#define PIN_BU2		PINA
#define PIN_ARB		PINL, PL1

//#define	INT_RTS		INT7
#define PIN_CTS		PINE, PE6

#define PIN_USRSW1	PINF, PF0
#define PIN_USRSW2	PINF, PF1
#define PIN_USRSW3	PINF, PF2
#define PIN_USRSW4	PINF, PF3
#define PIN_USRSW5	PINF, PF4
#define PIN_IGNINT	PINB, PB5
#define INT_IGN		ePINT5

#define UDRE UDRE0	// Same position/name for Atmega1280
#define ADCSR ADCSRA
// Primary Uart
#ifdef USE_UART2
/*#undef UBRR0  
#undef UBRR0L 
#undef UBRR0H 
#undef UDR0   
#undef UCSR0A 
#undef UCSR0B 
#undef UCSR0C 
# define UBRR0  _SFR_MEM16(0xD4)
# define UBRR0L _SFR_MEM8(0xD4)
# define UBRR0H _SFR_MEM8(0xD5)
# define UDR0   _SFR_MEM8(0XD6)
# define UCSR0A _SFR_MEM8(0xD0)
# define UCSR0B _SFR_MEM8(0XD1)
# define UCSR0C _SFR_MEM8(0xD2)*/

	#define PIN_RTS			PINB, PB4
	#define	INT_RTS			ePINT4
	#define DDR_CTS0		DDRB, PB0
	#define PORT_CTS0		PORTB, PB0
	#define SIG_UART0_TRANS SIG_USART2_TRANS
	#define SIG_UART0_RECV	SIG_USART2_RECV	
	#define SIG_UART0_DATA	SIG_USART2_DATA
#else
	#define PIN_RTS			PINE, PE7
	#define INT_RTS			eINT7
	#define DDR_CTS0		DDRE, PE6
	#define PORT_CTS0		PORTE, PE6
	#define SIG_UART0_TRANS SIG_USART0_TRANS
	#define SIG_UART0_RECV	SIG_USART0_RECV
	#define SIG_UART0_DATA	SIG_USART0_DATA
#endif

//#define COMM_RTS_INT	INT_RTS

#define SIG_UART1_TRANS	SIG_USART1_TRANS
#define SIG_UART1_RECV	SIG_USART1_RECV
#define SIG_UART1_DATA	SIG_USART1_DATA

// Flash Memory Restrictions
 #define FLASH_END		0x1FFFFF
//#define FLASH_END		0xFFFFFF

//---------------------- Output Definitions
#define AUX_OUT_12_SET_PWM(x)	timer_initialise_mode(3,x,TIMER_PWMFC)
#define AUX_OUT_1_TIMER			3
#define AUX_OUT_2_TIMER			AUX_OUT_1_TIMER
#define AUX_OUT_1_SET(x)		timer_3_pwm_A_set(x)
#define AUX_OUT_1_SET_VALUE(x)	timer_3_pwm_A_set_value(x)
#define AUX_OUT_1_STATUS		timer_status(3)
#define AUX_OUT_2_SET(x)		timer_3_pwm_B_set(x)
#define AUX_OUT_2_SET_VALUE(x)	timer_3_pwm_B_set_value(x)
#define AUX_OUT_2_STATUS		timer_status(3)

#define AUX_OUT_34_SET_PWM(x)	timer_initialise_mode(4,x,TIMER_PWMFC)
#define AUX_OUT_3_TIMER			4
#define TMR_OVER				eTimer4_Overflow
#define AUX_OUT_4_TIMER			AUX_OUT_3_TIMER
#define AUX_OUT_3_SET(x)		timer_4_pwm_A_set(x)
#define AUX_OUT_3_SET_VALUE(x)	timer_4_pwm_A_set_value(x)
#define AUX_OUT_3_STATUS		timer_status(4)
#define AUX_OUT_4_SET(x)		timer_4_pwm_B_set(x)
#define AUX_OUT_4_SET_VALUE(x)	timer_4_pwm_B_set_value(x)
#define AUX_OUT_4_STATUS		timer_status(4)

#define ADC_MAX				5000
#define ADC_MULT			13.0944
#ifndef ADC_INITIAL_REF
#define ADC_INITIAL_REF AREF

#define	PORT_TRCOE	PORTH, PH7
#define DDR_TRCOE	DDRH, PH7

#define THREAD_TIMER	eTimer1_CompareA
#define THREAD_TIMER_NO	1

#define UART0_RX_BUFFER_SIZE		0x1000	///< number of bytes for uart0 receive buffer

#endif
